发明名称 Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion
摘要 A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received. A link control unit is provided in which loop management is provided when the host is connected to a loop. Management of the loop includes implementing mechanisms to initiate acquisition of the loop and initiate a release of the loop in response to conditions in which data is received and transmitted by the host and by other nodes on the loop.
申请公布号 US6185620(B1) 申请公布日期 2001.02.06
申请号 US19980054849 申请日期 1998.04.03
申请人 LSI LOGIC CORPORATION 发明人 WEBER DAVID M.;HOGLUND TIMOTHY E.;JOHNSON STEPHEN M.;ADAMS JOHN M.;REBER MARK A.
分类号 G06F13/12;G06F13/36;H04L12/56;H04L29/06;(IPC1-7):G06F11/00;G06F9/46;H04Q11/04 主分类号 G06F13/12
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