| 摘要 |
<p>A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the externally applied system clock speed. The memory device (40) includes clock sensing circuitry (10) that receives the system clock signal [SYSCLK] and responsively produces a speed signal (SLOW<0:1>). The clock sensing circuitry [10] includes a plurality of series-connected time-delay circuits (14) through which a signal derived from the system clock signal (SYSCLK) propagates. The clock sensing circuitry (10) also includes a plurality of latch circuits (16), each coupled with a respective one of the time delay circuits (14) and latching the value of the signal reaching the respective time delay circuit (14). The memory device (40) also includes a control signal delay circuit (60) that receives an internal memory control signal and the speed signal (SLOW<0:1>), and responsively produces a delayed control signal having a time delay corresponding to the speed signal value. The control signal delay circuit (60) includes a plurality of series-connected time-delay circuits (62) and a selection circuit (64) that receives the speed signal (SLOW<0:1>) and correspondingly routes the memory control signal through the selected number of the time-delay circuits (62).</p> |
