| 摘要 |
A process for fabricating a DRAM cell, with an area equal to five times the minimum feature, squared, (5F2), has been developed. The process features the use of selectively formed, N+ single crystalline, silicon plugs, on underlying source/drain regions. The N+ single crystalline, silicon plugs, epitaxial deposited, are used to connect overlying crown shaped capacitor structures, to underlying source/drain region, as well as to connect a bit line metal structure, to another source/drain region.
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