| 摘要 |
A clock signal is frequency divide to generate a plurality of signals CK, CK' having different periods, and a plurality of the control signals C, TZS are generated from them. One of the control signals C, TZS is selected as control signal TZ1, depending on the comparison section T1-T4, so as to change the period of the control signal for each comparison section. The reference voltage and the input voltage are compared according to the control signal TZ1. The period of the control signal is made shorter at the comparison sections other than the section T2 which requires a longer comparison time for the stabilization of the reference voltage, due to the large difference of the former reference voltage and the present reference voltage.
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