发明名称 LSI ARRANGEMENT METHOD AND SYSTEM TAKING DELAY RESTRICTION INTO ACCOUNT
摘要 PROBLEM TO BE SOLVED: To constitute an LSI arrangement system, which can ensure a wiring efficiency and easily satisfy delay restriction by making a partitioning processing by the use of a high-performance min-cut algorithm, while estimating increase int he length of wiring due to position restrictions. SOLUTION: Check is made as to whether a connection to be noted is a position restriction connection connected to a certain cell having position restrictions. If the connection is not a position restriction connection, an ordinary cost calculation is made based on slack. If the connection is a position restriction connection, a critical path is extracted and a mapping processing is made for the extracted critical path to calculate the cost of the critical path. Whether the processing is finished to all the nets is checked. If the processing is finished for all the nets, a partitioning processing is executed so as to minimize cost. If the partitioning processing is finished, whether partitioning is sufficiently fine is checked, and if the partitioning becomes sufficiently fine, the processing is finished.
申请公布号 JP2001028395(A) 申请公布日期 2001.01.30
申请号 JP19990200299 申请日期 1999.07.14
申请人 FUJITSU LTD 发明人 KANAZAWA YUJI
分类号 H01L21/822;G06F17/50;H01L21/82;H01L27/04;(IPC1-7):H01L21/82 主分类号 H01L21/822
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