发明名称 METHOD FOR FORMING VERTICAL TRANSISTOR CMOS INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To integrate a vertical transistor by providing a device with a source extending portion and a drain extending portion, where the source extending portion and the drain extending portion in a semiconductor substrate are regulated by the thickness of the doped first and third layers of a material, and by providing the second layer with a place for a gate to be formed later. SOLUTION: The active region of a device is formed by depositing at least three kinds of layers on a substrate. The first and third layers among these layers are three kinds of layers and regulate a source-extending portion which extends in a plug of a semiconductor material or a drain-extending portion. That is, in the case where the source of the device is formed under a semiconductor plug, the first layer regulates the source extending portion and the third layer regulates the drain-extending portion. In the case where the drain of the device is formed under the semiconductor plug, the first layer regulates the drain-extending portion, and the third layer regulates the source extending portion. The thickness of the second layer regulates the length of gate of the device.
申请公布号 JP2001028399(A) 申请公布日期 2001.01.30
申请号 JP20000181209 申请日期 2000.06.16
申请人 LUCENT TECHNOL INC 发明人 HERGENROTHER JOHN MICHAEL;MONROE DONALD P
分类号 H01L21/336;H01L21/8238;H01L27/06;H01L27/092;H01L29/78;(IPC1-7):H01L21/823 主分类号 H01L21/336
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