| 摘要 |
A flash memory cell formed in a semiconductor substrate is disclosed. The cell includes an n-well formed within the substrate. Next, a p+ drain region is formed within the n-well. A floating gate is formed above the n-well being separated from the substrate by a thin oxide layer. The floating gate is formed adjacent to the p+ drain region. Finally, a control gate is formed above the floating gate, the floating gate and the control gate being separated by a dielectric layer. The new cell is read by measuring the GIDL current at p+/n-well junction, which is exponentially modulated by the floating gate potential (or its net charge). The new cell is programmed by band-to-band hot electron injection and is erased by F-N tunneling through the overlap area of floating gate and n-well.
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