Output line arrangement structure of row decoding array

摘要

The present invention relates to an output line arrangement structure of a row decoding array used to determine a word line address of a plurality of memory cell arrays in a semiconductor memory device. The present invention can decrease an area when arranging the memory array, and can implement a high speed operation according to load reduction of a word line control signal, by arranging a part of output lines at one side end portion of a memory array, and another part thereof at the middle portion of the memory array (bit line divider), in a bus structure of word line enable and disable signals used for the row decoding array (main word line and sub-word line array constitution).