| 摘要 |
A flash memory array having a reduced number of metal source lines and increased storage density. The cells are arranged in rows and columns, with the cells in a row having their control gates connected to a common word line and the cells in a column having their drains connected to a common bit line. All of the cell sources of the array are connected together with a combination of doped semiconductor and metal lines. The source metal lines are disposed generally in parallel with the bit lines. In order to reduce the number of source metal lines, the lines are spaced apart by, typically, eight, sixteen or more cell columns. The metal source lines define a sub-array therebetween. The array includes a decoder for accessing two cells in different columns of each sub-array during single reading and programming operations. Thus, each sub-array provides two bits of data rather than the customary one bit. The reduced number of metal source lines saves a significant amount of die area with a only a small sacrifice in increased effective source line resistance.
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