| 摘要 |
A new distributed control mechanism for managing bi-directional interfaces of symmetrical multiprocessor systems in such a manner as to minimize the latency to storage, yet fairly distribute the use of the interfaces amongst the various components.This bi-directional interface can be designed to perform with differing characteristics depending upon the direction of information flow. These characteristics are implemented into the control logic of the source and destination components interconnected by the bi-directional interface, thus yielding two interface behaviors using only one interface. Each component is able to track the state of the interface by using only its own request state in conjunction with the detected request state of the opposing component, when both units are operating under the joint control algorithm present in the control logic of the source and destination component. In this embodiment, there is no single bus arbiter to prioritize the bus interface transfers, rather both units on the bus operate together to schedule their own transfers based on the specific algorithm chosen for that bus interface. The joint control algorithm balances the biasing of the interfaces so that traffic in one direction is not "starved out" because of heavy traffic in the other direction. This approach also eliminates the need for transfer acknowledges which further enhances system performance and reduces unit to unit interconnections.
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