发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To form a wiring or an electrode with ohmic connection to a substrate, simultaneously with the formation of a low resistance upper layer wiring on a gate electrode. SOLUTION: In this manufacturing method, a first resist pattern 7 having an aperture 7a for exposing source/drain regions 5, 6 to expose the upper surface of a gate electrode 2 is formed and a second resist pattern 8 having the second apertures 8d, 8e, 8c for defining source/drain electrodes 10, 11 and upper layer wiring 9 is laminated on a first resist pattern. Next, the upper wiring 9 and source/drain electrodes 10, 11 are formed simultaneously with lift-off, using the first and second resist patterns 7, 8 as the masks.
申请公布号 JP2001028374(A) 申请公布日期 2001.01.30
申请号 JP19990200468 申请日期 1999.07.14
申请人 FUJITSU QUANTUM DEVICES LTD 发明人 MATSUDA HAJIME
分类号 H01L21/3205;H01L21/28;H01L21/338;H01L29/812;(IPC1-7):H01L21/338;H01L21/320 主分类号 H01L21/3205
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