Phase-locked loop with small phase error

摘要

A phase-locked loop for controlling the phase of an output signal S2 dependent on a reference signal S1 with only a small phase timing error has a sampling circuit for sampling the reference signal S1 with the output signal S2 and for generating a sampling signal S1A, a jitter modulation circuit (3) for generating a sampling signal S1AJ delayed by a defined time duration and for alternating output of the undelayed sampling signal S1A and the delayed sampling signal S1AJ, a phase detector for acquiring an average phase difference between the output signal S2 and the delayed and undelayed sampling signals S1A and S1AJ, and a controllable oscillator for generating the output signal S2 with a frequency that is controllable dependent on the average phase difference acquired by the phase detector.