| 摘要 |
An encoder for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal, the bitstream of the source signal being divided into smaller n-bit source words (x1, x2) which are converted by a logic circuit converter in the encoder into corresponding m-bit channel words, (y1, y2, y3). The conversion of each n-bit source word is parity preserving (see Table I and FIG. 1). The relations hold that m>n>=1, p>=1, and p can vary. Preferably, m=n+1. In order to comply with (d, k) runlength requirements, certain blocks of 2-bit source words are encoded into particular blocks of 3-bit channel words. A decoder is also disclosed for decoding a channel signal produced by the encoder. |
