| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a microcomputer which can eliminate the redundant waiting time between a CPU and a BCU and improves its total processing throughput. SOLUTION: A CPU 10 is prepared to issue an instruction with a single clock pitch together with a BCU 20 including a bus clock generation means 24 which inputs a CPU clock to be supplied to the CPU 10 as a BCU drive clock signal and then generates and outputs a bus clock BUSCLK having a cycle of >=2 times and also an integer multiple as much as the BCU drive clock signal. The means 24 outputs the bus clock only in its bus cycle.</p> |
