| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit in which the fluctuation of a generated clock can be reduced against the fluctuation of a power supply voltage. SOLUTION: A PLL circuit is provided with a phase comparator, a loop filter, and a voltage control transmitter including a voltage/current converting circuit for converting a control voltage outputted from the loop filter into current, and a CMOS ring oscillator 1 constituted of plural ring oscillators 5 having current sources corresponding to the output current. The voltage/ current converting circuit 7 uses a variable resistance changing according to the fluctuation of a power supply voltage as an element for deciding the output current.
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