VARIABLE DELAY CIRCUIT AND DELAY FINE ADJUSTMENT CIRCUIT

摘要

PROBLEM TO BE SOLVED: To obtain a convenient circuit by avoiding adding a mirror capacity in a state of closing a logical gate but adding the mirror capacity in a state of opening the logical gate so as to increase a delay time by the portion of the mirror capacity through the use of a switch signal for supplying the delay time to a second input terminal. SOLUTION: A load capacity circuit obtained by combining unit delay elements is provided at a signal transmission path between an input buffer IB and an output buffer OB used in common as a waveform forming circuit. An input signal which should be delayed is supplied to the input terminal 8 of the buffer IB to obtain a delayed output signal from the output terminal 9 of the buffer OB. In order to providing satisfactory linearity to variable delay time and simultaneously simplifying its switch control, a switch control signal 7 having a binary weight is used. In making only a signal C0 at a high level, a mirror capacity obtained by multiplying by a gain at a gate circuit G11 is added. The load capacity of an input buffer IB is increased with a minimum capacity as one unit by the combination of signals C0 to C2.