| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce clock rate and power consumption of a constituting element constituting an interface circuit by dividing the stream of input data into two separate binary streams, a having a phase difference of a half cycle. SOLUTION: An interface 11 includes a shift means 12 for separately transmitting the even-number bit and obb-number bit of input data in two serial streams 13 and 14 by the phase difference of a half cycle with respect to an internal clock, a means 15 for comparing even- and odd-number continuous bits transmitted from the streams 13, 14 by each pair so as to lead out as signal STROBE-TX from the result, and a temporal reset means 16. Namely, this interface device divides an input data stream into two streams by the phase difference of a half cycle, so as to serially transmit the even- and odd-number bits of input data. The rate of each serious stream corresponds to half the binary rate of received input data.</p> |
