| 摘要 |
PROBLEM TO BE SOLVED: To finely adjust a delay value by converting an adjusted delay value calculated by simulating a wiring delay after automatic wiring into a capacitance value, and forming a capacitance pattern having the magnitude corresponding to the capacitance value on delay adjusting cells. SOLUTION: A critical path is detected simultaneously with circuit integration (S1) and delay adjusting cells are arranged based on the critical path and automatic layout cell arrangement (S2). Then layout pattern data are prepared (S3) and the delay at every wiring is extracted (S4). After the delay is extracted, the non-conformable spot of timing and a delay value are acquired by simulating the delay of actual wiring using the extracted delay of the wiring (S5). Then the delay value is converted into a capacitance value (S6) and the coordinate data of the capacitance pattern for securing the capacitance value are calculated (S7). Finally, the coordinate data of the capacitance pattern are put together with layout pattern data (S8).
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