发明名称 EFFICIENT SUB-INSTRUCTION EMULATION IN VLIW PROCESSOR
摘要 PURPOSE: A method and an apparatus to efficiently emulate a sub-instruction is provided by combining stored result from at least one sub-instruction emulated in a software with a result from the residual sub-instructions executed in a hardware. CONSTITUTION: A VLIW processor (101) detects an exceptional state to report it to a pipeline control unit (108). Then, the contents of exception registers (126, 128, 130 and 132) are sent via OR gates (135, 136, 138, 140 and 144) to form an exception signal (146), which is sent to a pipeline control unit (108). The result of the exceptional state is stored in an external memory. In this case, this system next stores the pattern of an enable signal concerning all the residual sub-instructions, which are not emulated, in an instruction break point mask register in the unit (108).
申请公布号 KR20010006789(A) 申请公布日期 2001.01.26
申请号 KR20000012374 申请日期 2000.03.13
申请人 SUN MICROSYSTEMS, INC. 发明人 TREMBLAY MARC;JOY WILLIAM N
分类号 G06F9/455;G06F9/30;G06F9/318;G06F9/38;(IPC1-7):G06F9/455 主分类号 G06F9/455
代理机构 代理人
主权项
地址