| 摘要 |
PROBLEM TO BE SOLVED: To facilitate execution not in order and instruction cancellation while accurately maintaining a set machine state by providing prefetch instruction transfer paths for a main and a target instruction stream respectively. SOLUTION: Each memory access processed by an MCU 110 is related to one of ports 146n-0 so as to transmit access to a main system memory bus 162 requested for access to an MAU 112. Once a connection for data transfer is established, the MCU 110 passes control information to a CCU 106 through a control bus 140, and data transfer is started between an instruction cache 132 or data cache 134 and the MAU 112 through a corresponding port, 146n-0. The MCU 110 neither stores nor latches data halfway in the transfer between the CCU 106 and MAU 112 actually. Namely, a transfer wait time is minimized and the need to trace and manage only one piece of data present at the MCU 110 is eliminated. |
