CHIP PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURE THEREOF

摘要

PROBLEM TO BE SOLVED: To provide a chip package substrate by which product yield can be improved by preventing formation of fuzz and a wiring film can be divided at the same time of completion of slits by providing conducting wires for electroplating in slits. SOLUTION: This substrate structure is formed by compression-bonding a multilayer wiring film 32 and an insulating film 34. Each wiring film 32 has a plurality of interconnect lines 44. The insulating film 34 is disposed between the wiring films 32 to insulate the films from each other. The substrate structure is provided with a plurality of via holes 36 and connected to a conducting wire film 48 for electroplating. A metal plating film 40 is provided in the periphery of each via hole 36. A hole filling material 42 is filled inside the metal plating film 40. Slots 54 are provided in the wiring film on the substrate structure surface. The plurality of wiring films have further a plurality of first contacts 44a and second contacts 44b. The plurality of first contacts are provided adjacent to the slots 54. The plurality of wiring films electrically connected to the plurality of first contacts 44a are extended to part of the plurality of via holes 36. The plurality of via holes 36 are placed in the periphery of the slots 54. Thus, part of the metal plating film 40 is exposed inside the slot 54.