TIMING SIGNAL GENERATING CIRCUIT, DLL CIRCUIT, SEMICONDUCTOR MEMORY, AND VARIABLE DELAY CIRCUIT

摘要

PROBLEM TO BE SOLVED: To generate a highly accurate timing signal by accelerating transition to a second level in a signal transition accelerating circuit, when a timing signal set to a first level by an active circuit is transited to a second level by a passive circuit. SOLUTION: A DLL circuit of a SDRAM is provided with a pseudo interface circuit section 3c as a timing signal generating circuit. Also, the pseudo interface circuit section 3c is provided with a signal transition accelerating circuit 12. When an internal clock signal CK is on an H level from an L level, the signal transition accelerating circuit 12 draws out electric charges charged to a capacitor C21 only during a predetermined fixed time. Therefore, a waveform of fall of a pseudo I/O interface signal dDQ of which a level of theoretical amplitude is set by resistors R21, R22 is made steep by drawing out electric charges of the capacitor 21, a highly accurate pseudo I/O interface signal dDQ can be generated.