| 摘要 |
PROBLEM TO BE SOLVED: To obtain an improved cache sub-system and a cache control circuit by comprising a terminal means receiving an input signal including a mode signal indicating a clock signal and plural cache functions being able to operate, and a logic circuit performing a cache function selected by responding to a mode signal during a single clock cycle. SOLUTION: A word line driver circuit is provided with a terminal 201 arranged to that a WLRSTB(word line reset bar) signal is applied to a gate terminal of a PFET 203. Gate terminals of NFET 209, 211, 213 are arranged so that they receives an EASEL (effective address) signal, an inverted EMATCHB (effective address match) signal, and a clock signal C2 respectively. A common paint of a PFET 219 and an NFET 221 are connected to input of a common node 207 and an inverter 223. The inverter 223 supplies an output signal EMATCHWL (effective address matched word line). |
