发明名称 BIAS CURRENT CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a bias current circuit whose current consumption is small and small in fluctuation of a load current even when noise is superimposed upon a power source. SOLUTION: A source of a PMOS 19 is connected to a high potential side Vcc of a power source E, a drain of the PMOS 19 is connected to a source of a PMOS 18 of an output transistor, a drain of the PMOS 18 is connected to a differential amplifier or a load 60 of a comparator, the drain of the PMOS 19 is connected to a high potential side of a temperature compensation circuit 50, a gate of the PMOS 18, an end of a capacitor 17 and a drain of a PMOS 11 which constitutes a temperature compensation circuit 50 are connected with one another, and other end of the capacitor 17 is connected to a ground 101. It is possible to attain reduction of a current consumption of the bias current circuit by making an Iref 20 and an Iref 30 zero when this bias current circuit is interrupted.
申请公布号 JP2001022458(A) 申请公布日期 2001.01.26
申请号 JP19990195464 申请日期 1999.07.09
申请人 FUJI ELECTRIC CO LTD 发明人 NAKAMORI AKIRA
分类号 G05F3/26;(IPC1-7):G05F3/26 主分类号 G05F3/26
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