| 摘要 |
PURPOSE: To reduce power consumption of a system which is equipped with plural synchronous memories. CONSTITUTION: When a clock enable signal CKE is inputted to an input buffer circuit 11a, a power-down clock PWDNCLK is outputted from a power-down control circuit 12, and input buffer circuits 11b, 11c and an input buffer activating circuit 13 are activated. The input buffer circuits 11b, 11c input respectively a clock signal CLK and a chip select signal CSB to output respectively an internal clock signal ICLK and an internal chip select signal ICSB which are synchronized with each other. The input buffer activating circuit 13 outputs a power-down signal PWDNB which becomes high in synchronization with the falling of the internal chip select signal ICSB. Thus, only an input buffer circuit 11e of a synchronous memory corresponding to the chip select signal CSB inputs a command CMDB.
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