| 摘要 |
<p>A bus and associated logic employ a master/slave communication protocol and unidirectional point-to-point connections. Unidirectional address lines (100) carry address signals from a bus master (28) to bus slaves. One set of unidirectional data lines (88) carry data from the master to the slaves, and another set (78) carries data from the slaves to the master. The master initiates a bus transaction by asserting a request signal and placing an address on the address lines (100). A slave device responds by returning an acknowledge signal. The master maintains the address and the request on the bus until one clock cycle after receiving the acknowledge signal. For a read, the data is returned in the cycle following the acknowledge signal. For a write, the master places the write data on the outgoing data lines (88) and maintains the data value on the bus until one cycle after the acknowledge signal. Additionally, the master deasserts the request signal for at least one cycle between bus transactions.</p> |
