| 摘要 |
<p>A data transfer control device capable of reducing a firmware processing overhead and implementing a fast data transfer, and an electronic apparatus. An IEEE-1394-standard data transfer control device, wherein the header of a packet is written in a header area, the ORB (SBP-2 data) of a packet in an ORB area, and the stream (application layer data) of a packet in a stream area. In the stream area, hardware performs an area management by means of a full signal and an empty signal. Instruction information is included in the transaction label (t1) of a requested packet, and a packet header, ORB and stream of a packet are written in an area designated by means of designation information contained in t1 when a response packet is received. Registers (TSR, TER) for storing addresses (TS, TE) for ensuring a transmission area in a stream area, and registers (RSR, RER) for storing addresses (RS, RE) for ensuring a reception area are provided.</p> |
