发明名称 Information processing system
摘要 <p>An information processing system comprises: a common bus; a processor (1) connected to the common bus; and a plurality of peripheral devices (19) connected to the common bus; wherein when one of the peripheral device (16, 19) issues a request for the right to use said common bus, a bus-use-right request signal (HREQ#) is outputted to said main processor, the right to use said system bus is assigned to said peripheral device (16, 19) which has outputted said bus-use-right request signal (HREQ#) after a bus-use-right permission signal (HACK#) is outputted in response to said bus-use-right request signal (HREQ#) by said processor (1), and said peripheral device (16, 19) is qualified to function as a bus master, and when said peripheral device (16, 19) becomes inoperative to said common bus after outputting said bus-use-right request signal (HREQ#), said bus-use-right permission signal (HACK#) outputted by said processor (1) is detected, and said bus-use-right request is released after the confirmation of the assignment of the right to use said system bus according to said bus-use-right permission signal (HACK#). &lt;IMAGE&gt;</p>
申请公布号 EP1071020(A2) 申请公布日期 2001.01.24
申请号 EP20000118060 申请日期 1992.12.10
申请人 FUJITSU LIMITED 发明人 IINI, HIDEYUKI;TAKAHASHI, HIROMASA;FUJIYAMA, HIROYUKI;KUROIWA, KOICHI;SHIRASAWA, KENJI
分类号 G06F13/16;G06F13/364;(IPC1-7):G06F13/364 主分类号 G06F13/16
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