发明名称 Input stage with dynamic hysteresis
摘要 A circuit for shifting the triggering threshold of a stage (MP1,MN1) having an input coupled to a circuital node (OUT), following the sensing of a switching phase of said node from a logic state to another and for the remaining duration of the switching phase, produces a hysteresis effectively greater than the maximum theoretical limit of hysteresis admitted by the triggering threshold of the stage (MP1,MN1) coupled to said circuital node. The circuit comprises at least two switches, a first switch (MP2) connected in an electric path between said circuital node (OUT) and a supply rail (Vdd) and the second switch (MN2) connected in an electric path between said circuital node (OUT) and ground; at least a generator (P1,P2) of a single pulse of duration equal or longer than the duration of the rise time and of the fall time of the voltage on said circuital node, and shorter than the minimum time of persistence at a certain logic state of said circuital node (OUT), having an input coupled to said circuital node (OUT) and generating said single pulse upon sensing a switching from a logic state to another of said circuital node. Means coupled to an output of said pulse generator and to the control nodes of said switches configure the switches (MP2,MN2) in a state such to maintain the new logic state assumed by said circuital node (OUT) for the duration of said single pulse. <IMAGE> <IMAGE>
申请公布号 EP1071215(A1) 申请公布日期 2001.01.24
申请号 EP19990830457 申请日期 1999.07.19
申请人 STMICROELECTRONICS S.R.L. 发明人 FUCILI, GIONA
分类号 H03K19/00;H03K19/017 主分类号 H03K19/00
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