发明名称 |
Processor E-unit to I-unit interface instruction modification with E-unit opcode computer logic in the unit |
摘要 |
A computer processor which has a apparatus in its Execution Unit (E-unit) that detects a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer provides a method for alleviating design deficiencies in the processor. The E-unit further contains a mechanism for transmitting the opcode and a desired action back to the Instruction Unit (I-unit) where it may be compared with the next instruction that is decoded. Furthermore, the E-unit opcode compare logic contains a mechanism for breaking infinite loops that may result. This E-unit opcode compare mechanism, may also be used for other purposes such as detecting invalid opcodes and other exception checking since it may allow for a faster cycle time of the processor than if this logic were implemented in the I-unit.
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申请公布号 |
US6178495(B1) |
申请公布日期 |
2001.01.23 |
申请号 |
US19980070537 |
申请日期 |
1998.04.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SLEGEL TIMOTHY JOHN;CHECK MARK ANTHONY |
分类号 |
G06F9/30;G06F9/318;G06F9/38;(IPC1-7):G06F9/30;G06F9/302 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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