Semiconductor memory device comprised of a double data rate-synchronous dynamic random access memory

摘要

A semiconductor memory device which enables holding of two or more addresses and selecting of an address output corresponding to kinds of commands with a sufficient operational margin. The semiconductor memory device of the present invention is so configured that a command decoder generates a first controlling signal after a first period following the inputting of a read command, a second controlling signal after a second period following the inputting of a write command, and an operation instructing signal to be fed to a column control circuit in response to first and second controlling signals, and a burst counter makes an input address delayed by first and second periods and outputs the address delayed by the first period as a read address in response to a first controlling signal and the address delayed by the second period as a write address in response to a second controlling signal.