| 摘要 |
A DRAM memory saves on the overall power consumed by the whole device by skipping unnecessary read, write, and refresh cycles of the internal memory core. Because each such cycle costs power, skipped cycles save power. Specifically, read cycles are not always automatically followed by write-back cycles that restore the read-data, e.g. due to the destructive-read nature of the DRAM. Such write-back cycles are only allowed when they can be postponed no longer, and the data written are actually used sometime later. Data that needs only to be read back once, and that have thereby served their purpose, are not written-back. Simple refresh cycles involving unused rows, or rows that have been destructively read and not yet written-back, are skipped and not refreshed. Data rows that are read from the memory core are held in the peripheral circuits in a way that simulates a cache. All the external byte and bit accesses that can be supported by the whole row in cache are serviced without read or write cycles to the memory core.
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