| 摘要 |
A memory structure for speeding up data access is disclosed. The memory structure has a row decoder and a column decoder to decode the address in the address bus for addressing the memory cells. A plurality of data latch units, each having at least two latches, are provided to optionally latch the data of the memory cells addressed by the row decoder into one of the latches of each data latch unit. A compare and select logic unit determines whether the data of the memory cells addressed by the row addresses is stored in the plurality of data latch units. If not, one of the latches in each data latch unit is selected for latching the data of the memory cells addressed by the row address. Because data of multiple rows of memory cells can be stored in the data latch units, a high probability exists to have data and instruction code to be accessed stored in the data latch units whereby the speed of memory access is greatly increased.
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