| 摘要 |
A gate wire including a gate line and a gate electrode and a common signal line are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal line. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer of the gate electrode, a source and a drain electrode thereon and a data line connected to the source electrode on the gate insulating layer are formed. A protection insulating layer is formed on the data line and the source and the drain electrodes. Common electrodes that are connected to the common signal line and pixel electrodes, which are connected to the drain electrode, are formed thereon. An alignment layer, which is in direct contact with the common electrodes and the pixel electrodes, is formed in pixel region where the common electrodes and the pixel electrodes are formed. The thickness of the pixel electrodes and the common electrodes is equal to or less than 1,000 Å with a taper angle.
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