| 摘要 |
In a synchronizing system, a CRC bit end judging circuit judges an end of a CRC bit of the demodulated signal from the demodulating circuit to produce a CRC bit end signal. A RSSI detecting circuit detects a RSSI level of the received signal to produce a RSSI level signal. An edge detecting circuit compares the RSSI level with a predetermined threshold level to produce a level compared result signal when the RSSI level is greater than the predetermined threshold level. The edge detecting circuit masks, in a predetermined time interval, the level compared result signal in response to both of the CRC bit end signal and the level compared result signal. The edge detecting circuit produces a trigger signal in response to the level compared result signal after the predetermined time interval. A bit synchronous circuit produces, in response to the trigger signal, the bit synchronous signal. A bit synchronous correcting circuit corrects the bit synchronous signal to produce and supply a bit synchronous correct signal to the demodulating circuit.
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