| 摘要 |
A process for forming a self-aligned BJT (bipolar junction transistor) is disclosed. Conventional front end processes are used to form an N+ layer on a substrate. An N-type collector region is then formed followed by formation of isolation regions on the substrate surface. A deep collection connector region is formed by ion implantation into the N-well. Next, a P base region is formed by ion implantation. An undoped polysilicon (polycide) layer is then deposited on the surface of the substrate. Thereafter, a dielectric layer, which preferably cannot be oxidized, is deposited on top of the undoped polysilicon (polycide) layer. The dielectric layer is then patterned to form a dielectric emitter. Nitride spacers are then formed on the sidewalls of the dielectric emitter. The polysilicon (polycide) layer is then heavily doped with P-type impurities except in the area of the dielectric emitter and nitride spacers. An oxide layer is then grown on the surface of the P+ doped polysilicon (polycide) layer and the nitride spacers are then removed. The oxide layer is also removed except from the emitter-base regions. Next, the dielectric emitter and thermally grown oxide layers are then used as a mask through which the P+ polysilicon (polycide) layer is etched away. The dielectric emitter and thermally grown oxide layers are then removed. The narrow gaps, that have been etched between the polysilicon (polycide) layer and the undoped polysilicon (polycide) layer, are then filled with a dielectric. The undoped polysilicon (polycide) regions are then heavily doped with N-type impurities. The impurities are then thermally driven out from the polysilicon (polycide) layer to the silicon substrate. Lastly, the conventional back end processes are followed which include ILD layer deposition and planarization, contact opening, metal deposition and patterning.
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