发明名称 Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor
摘要 A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is calculated directly and concurrently from the leading zeros string and the leading ones strings prior to a determination of a sign of an output of the positive sum and the negative sum.
申请公布号 US6178437(B1) 申请公布日期 2001.01.23
申请号 US19980139940 申请日期 1998.08.25
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DHONG SANG HOO;NGO HUNG CAI;NOWKA KEVIN JOHN
分类号 G06F7/50;G06F7/74;(IPC1-7):G06F7/42;G06F7/00 主分类号 G06F7/50
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