| 摘要 |
A digital PLL circuit having an impulse noise remover for removing an impulse noise component from an external reference clock signal and for outputting an internal reference clock signal having had noise removed therefrom. The acquisitor and the phase detector receive the internal reference signal. The acquisitor generates a reset signal according to the external reference clock signal and according to an act mode signal for synchronizing with an external system. A phase detector, which is reset by the reset signal, is operative for comparing the phase of the external reference clock signal with that of a clock signal self-divided at the same frequency as the external reference clock signal. The phase detector generates a phase detection signal. A frequency synthesizer generates a corrected clock signal, by changing the division ratio of a system clock signal according to the phase detection signal and an act clock signal, to generate a locked final output.
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