| 摘要 |
A phase-locked loop (PPL) utilizing a RAM is disclosed. The RAM is provided to store a reference clock and a clock to be controlled. The PLL further comprises a voltage-controlled oscillator section controls a phase of the clock to be controlled. The PLL further comprises a controller for retrieving, from the RAM, data of said reference clock and said clock to be controlled. The controller determines a phase difference between said reference clock and said clock to be controlled. Additionally, the controller generating a control signal so as to reduce said phase difference and applying said control signal to said voltage-controlled oscillator section.
|
