CIRCUIT BLOCK FOR CLOCK TREE SYNTHESIS AND CLOCK TREE CIRCUIT AND ITS DESIGN METHOD

摘要

PROBLEM TO BE SOLVED: To solve a clock skew problem by supplying a clock signal to a different-edge-trigger-type logic circuit group by a single clock tree circuit. SOLUTION: In a logic circuit 1, a positive-edge-trigger-type scan path flip- flop group (P.F/F group) 10, and a negative-edge-trigger-type scan path flip-flop group (N.F/F group) are mixed. In a normal operation mode, a clock tree circuit supplies a system clock signal CLK3 to the P.F/F group 10 and the N.F/F group 11 as clock signals 74 and 7 5. In a scan path test operation mode, the clock tree circuit supplies a scan path shift clock signal SCLK5 to the P.F/F group 10 as a clock signal 74, and supplies a signal where the SCLK5 is inverted to the P.F/F group 11 as a clock signal 75. The clock tree circuit thus configured is subjected to clock tree synthesis processing as a single clock tree.