| 摘要 |
PROBLEM TO BE SOLVED: To discriminate the phase relation of a clock signal to an input signal. SOLUTION: This digital data processor is provided with a first FF 8 for fetching and outputting the signal value of the input signal synchronously with the clock of the clock signal, a delay circuit 10 for delaying the clock signal for operation unstable time resulting from adding the setup time and hold time of the first FF and outputting it as a delaying clock signal, a second FF 11 for fetching the signal value of the input signal synchronously with the clock of the delayed clock signal, and outputting it, an exclusive OR circuit 9 for exclusively ORing the output signal of the first FF and the output signal of the second FF and outputting the result as an exclusive OR signal, a third FF 12 for fetching the exclusive OR signal synchronously with the clock of the clock signal and outputting it and a discrimination means 15 for discriminating the propriety of the phase relation of the clock signal to an input FF 4 on the basis of the output signal of the third FF. |
