摘要 |
<p>PROBLEM TO BE SOLVED: To accelerate the transfer speed of a signal in a memory module and to reduce the power consumption. SOLUTION: This memory module 3 consists of a memory controller 3a and memories 4 to 7 and has a configuration in which the semiconductor chips of the memories 4 to 7 are laminated on the semiconductor chip of the controller 3a. The controller 3a consists of AND circuits AD1 to AD16, only an AND circuit corresponding to a memory selected by any of chip enable signals CE1 to CD4 performs input-output of a data signal, an address signal or the like, and the other memories reduce parasitic capacitance to be driven in the module 3 and accelerate a memory system by electrically disconnecting a connection path.</p> |