TIME-DIGITAL CONVERTER, SYNCHRONOUS CIRCUIT USING THE CONVERTER AND METHOD THEREFOR

摘要

PROBLEM TO BE SOLVED: To minimize a phase difference of an internal clock signal to a reference clock signal by generating a synchronization delay control signal group for controlling a delay reflecting circuit so that the phase difference between a feedback signal and the internal clock signal for generating an initial internal clock signal and an auxiliary clock signal is reduced. SOLUTION: A delay reflecting circuit 207 delays an auxiliary clock signal FCLK 01 of another output signal of a clock driving part 205 just for a second delay amount and generates a feedback signal FCLK11. The second delay amount is equal to a delay amount by a modeled resistor and a capacitance. Here, the auxiliary clock signal FCLK01 can be a signal equal to an initial internal clock signal OICLK1. The second delay amount at the delay reflecting circuit 207 is controlled based on a delay control signal group GDC outputted from a time-digital converter (TDC) 211.