| 摘要 |
PROBLEM TO BE SOLVED: To obtain a gate array, having a layout structure which realizes min. gate width requiring only low power consumption, even in a standard cell having a fixed number of horizontal wiring grids. SOLUTION: This gate array comprises standard cells, composed of n-wells 3 formed on a p-type semiconductor substrate, a rectangular pattern of p-type field diffusions 6 formed therein, p-type FETs having a common source or drain in the diffusions, a rectangular pattern of n-type field diffusions 7, and n-type FETs having a common source or drain in the diffusions, and the first and second conductive field effect transistors constituting the standard cell have gate widths reduced at the channel regions, as compared with the rectangular pattern height specifying the field diffusion.
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