发明名称 EXPOSURE METHOD, RETICULE AND MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide an exposure method capable of reducing arraying errors so as to effectively use the shot area of an aligner. SOLUTION: A mark for measuring arraying errors to an adjacent patter is formed in the shot area of reticule (step S1) to expose and develop the mark on a wafer (step S2). Then, the arraying error of the mark on the wafer is measured (step S3) to calculate four error components (step S4). Finally, the aligner is corrected by using the calculated four error components (step S7). An arraying error at exposure to be conducted next is reduced.
申请公布号 JP2001015419(A) 申请公布日期 2001.01.19
申请号 JP19990186713 申请日期 1999.06.30
申请人 TOSHIBA CORP 发明人 TAWARAYAMA KAZUO;KONO TAKUYA
分类号 H01L21/027;G03F7/20;G03F9/00 主分类号 H01L21/027
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