| 摘要 |
PROBLEM TO BE SOLVED: To improve a system performance by making an analog/digital(A/D) converting part for dispatching a signal, for which a received signal is sampled and digitized, to a code division multiple access communication decoding means receive a sampling clock capable of phase control at a sampling frequency. SOLUTION: A parallel correlator configuration part 9 is composed of plural sets of correlators. Each of sets is provided with three correlators W, E and L and one set of correlators is prepared for each detection strength signal path. Outputs from these sets of correlators are dispatched to a DLL control configuration part 22. The DLL control configuration part 22 supplies an input signal to a clock/spread waveform generating part 24 and controls the phases of a clock signal and a spread waveform for the sets of respective correlators, an A/D converting part 6 and an FIR filter 8. This generating part 24 controls the phase of the clock signal, sends the clock signal to the A/D converting part 6 and the FIR filter 8 and sends the clock signal/spread waveform to correlators 10-20. |
