| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL synthesizer capable of suppressing a change of a PLL closed loop gain and suppressing a fluctuation of lock time or increase of a phase error even when a system frequency to be used is changed. SOLUTION: In this PLL synthesizer, a closed loop is composed of a reference signal generator 1, a variable frequency divider 2 for reference signal, a phase comparator 5, a loop filter 6, a voltage controlled oscillator 3 and a frequency divider 4 for oscillation signal. A control part 7 outputs a system frequency band switching signal FSL for selecting any frequency band at the time of system switching corresponding to a system to be used. The phase comparator 5 detects a phase error between a reference signal fr2 for phase comparison and a frequency dividing signal (f)out/N, switches a current gain corresponding to the system frequency switching signal FSL and outputs a current corresponding to the phase error. |
