发明名称 BUFFERING SYSTEM BUS FOR EXTERNAL-MEMORY ACCESSES
摘要 A computer system (AP1) includes a processor (11), a cache (13), a system bus (19), a memory-control subsystem (21), an external memory bus (23), RAM memory (25), and flash memory (27). All but the last three are fabricated on a single ASIC. The memory control subsystem includes a RAM controller (31), a flash-memory controller (33), and a memory interface (37) between the controllers and the memories. In addition, the memory-control subsystem includes a system-bus FIFO write buffer (35). During an external-memory access, the request information is transferred from the system bus to the system-bus buffer instead of directly to the memory interface. The system-bus buffer stores address data, content data (in the case of a write request), and control data. In turn, the control data is forwarded to the appropriate controller and the address data and the content data are forwarded to external memory bus. Note that only one system-bus write buffer is required despite the plural memory controllers. While the processor write buffer frees the processor for other tasks while a write operation is being completed, the system-bus write buffer frees the system bus for other tasks while a write operation is being completed. The system-bus buffer thus allows other operations to utilize the system bus during an external-memory access.
申请公布号 WO0104763(A1) 申请公布日期 2001.01.18
申请号 WO2000US16045 申请日期 2000.06.12
申请人 PHILIPS ELECTRONICS NORTH AMERICA CORPORATION 发明人 LIEWEI, BAO
分类号 G06F12/00;G06F13/16;(IPC1-7):G06F13/16 主分类号 G06F12/00
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