| 摘要 |
<p>A synchronous delay circuit system comprises an input buffer having a first delay time and receiving an external clock, a clock driver having a second delay time and for an internal clock, a dummy delay circuit having a delay time equal to a sum of the first delay time and the second delay time, a first delay circuit array formed of a predetermined number of delay circuits having a predetermined delay time, for measuring a time difference of a constant period from an output of the dummy delay circuit, a second delay circuit array formed of a predetermined number of delay circuits having a predetermined delay time, for reproducing the measured time difference to output the reproduced time difference to the clock driver, a circuit for measuring the frequency of the external clock to output a frequency measurement signal, and a delay time control circuit responding to the frequency measurement signal to control the traveling speed of a pulse or a signal edge in the first delay circuit array and in the second delay circuit array thereby to control the above mentioned predetermined delay time. <IMAGE></p> |
