| 摘要 |
In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors connected to each of the metal lines. The program disturb inhibited is connected to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. By combining the program disturb inhibit unit with the memory array, a conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, allowing the cell size to be reduced.
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